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AgeCommit message (Expand)Author
2023-06-13target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li
2023-06-13target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li
2023-06-13target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li
2023-06-13target/riscv: Fix target address to update badaddrWeiwei Li
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li
2023-06-13target/riscv: smstateen knobsMayuresh Chitale
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale
2023-06-13target/riscv: smstateen check for fcsrMayuresh Chitale
2023-06-13target/riscv: Update cur_pmmask/base when xl changesWeiwei Li
2023-06-13target/riscv: Fix pointer mask transformation for vector addressWeiwei Li
2023-06-13target/riscv: Deny access if access is partially inside the PMP entryWeiwei Li
2023-06-13target/riscv: Separate pmp_update_rule() in pmpcfg_csr_writeWeiwei Li
2023-06-13target/riscv: Flush TLB only when pmpcfg/pmpaddr really changesWeiwei Li
2023-06-13target/riscv: Flush TLB when pmpaddr is updatedWeiwei Li
2023-06-13target/riscv: Update the next rule addr in pmpaddr_csr_write()Weiwei Li
2023-06-13target/riscv: Flush TLB when MMWP or MML bits are changedWeiwei Li
2023-06-13target/riscv: Remove unused paramters in pmp_hart_has_privs_default()Weiwei Li
2023-06-13target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabledWeiwei Li
2023-06-13target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li
2023-06-13target/riscv: Make the short cut really work in pmp_hart_has_privsWeiwei Li
2023-06-13target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmpWeiwei Li
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: validate extensions before riscv_timer_init()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: add priv_spec validate/disable_exts helpersDaniel Henrique Barboza
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li
2023-06-13target/riscv: Mask the implicitly enabled extensions in isa_string based on p...Weiwei Li
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza
2023-06-13target/riscv/cpu.c: remove set_priv_version()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: remove set_vext_version()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_v()Daniel Henrique Barboza
2023-06-13target/riscv: Move zc* out of the experimental propertiesWeiwei Li
2023-06-13target/riscv/vector_helper.c: skip set tail when vta is zeroDaniel Henrique Barboza
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson
2023-06-05tcg: Split out tcg/oversized-guest.hRichard Henderson
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza
2023-05-05target/riscv: add query-cpy-definitions supportDaniel Henrique Barboza
2023-05-05target/riscv: add CPU QOM headerDaniel Henrique Barboza
2023-05-05target/riscv: Reorg sum check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Reorg access check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Merge checks for reserved pte flagsRichard Henderson
2023-05-05target/riscv: Don't modify SUM with is_debugRichard Henderson
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