slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-03-26	target/riscv: Fix wrong expanding for c.fswsp	Kito Cheng
2019-03-22	target/riscv: Zero extend the inputs of divuw and remuw	Palmer Dabbelt
2019-03-19	target/riscv: Remove unused struct	Alistair Francis
2019-03-19	RISC-V: Update load reservation comment in do_interrupt	Michael Clark
2019-03-19	RISC-V: Convert trap debugging to trace events	Michael Clark
2019-03-19	RISC-V: Add support for vectored interrupts	Michael Clark
2019-03-19	RISC-V: Change local interrupts from edge to level	Michael Clark
2019-03-19	RISC-V: linux-user support for RVE ABI	Kito Cheng
2019-03-19	RISC-V: Allow interrupt controllers to claim interrupts	Michael Clark
2019-03-19	riscv: pmp: Log pmp access errors as guest errors	Alistair Francis
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson
2019-03-19	RISC-V: Add debug support for accessing CSRs.	Jim Wilson
2019-03-19	RISC-V: Fixes to CSR_* register macros.	Jim Wilson
2019-03-17	target/riscv: Fix manually parsed 16 bit insn	Bastian Koppelmann
2019-03-13	target/riscv: Remove decode_RV32_64G()	Bastian Koppelmann
2019-03-13	target/riscv: Remove gen_system()	Bastian Koppelmann
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64D insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64F insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64A insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann
2019-02-11	target/riscv: fix counter-enable checks in ctr()	Xi Wang
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark
2019-02-11	RISC-V: Add misa.MAFD checks to translate	Michael Clark
2019-02-11	RISC-V: Add misa to DisasContext	Michael Clark
2019-02-11	RISC-V: Add priv_ver to DisasContext	Alistair Francis
2019-02-11	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark
2019-02-11	RISC-V: Implement mstatus.TSR/TW/TVM	Michael Clark