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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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vector_helper.c
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2022-06-10
target/riscv: rvv: Add tail agnostic for vector reduction instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector load / store instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vv instructions
eopXD
2022-06-10
target/riscv: rvv: Rename ambiguous esz
eopXD
2022-06-10
target/riscv: rvv: Prune redundant access_type parameter passed
eopXD
2022-06-10
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
eopXD
2022-04-22
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
Weiwei Li
2022-04-22
target/riscv: optimize helper for vmv<nr>r.v
Weiwei Li
2022-04-06
Replace config-time define HOST_WORDS_BIGENDIAN
Marc-André Lureau
2022-02-16
target/riscv: Fix vill field write in vtype
LIU Zhiwei
2022-01-21
target/riscv: Adjust vector address with mask
LIU Zhiwei
2022-01-21
target/riscv: Fix check range for first fault only
LIU Zhiwei
2022-01-21
target/riscv: Adjust vsetvl according to XLEN
LIU Zhiwei
2022-01-21
target/riscv: Split out the vill from vtype
LIU Zhiwei
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
2021-12-20
target/riscv: rvv-1.0: implement vstart CSR
Frank Chang
2021-12-20
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
2021-12-20
target/riscv: rvv-1.0: widening floating-point/integer type-convert
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point min/max instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width floating-point reduction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point slide instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: slide instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: mask-register logical instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point compare instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer comparison instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing integer right shift instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer extension instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: register gather instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: set-X-first mask bit instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: find-first-set mask bit instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: count population in mask instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
Frank Chang
2021-12-20
target/riscv: rvv-1.0: load/store whole register instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: fault-only-first unit stride load
Frank Chang
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