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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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vector_helper.c
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Author
2021-05-11
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
2021-05-11
target/riscv: fix vrgather macro index variable type bug
Frank Chang
2021-05-11
target/riscv: Fixup saturate subtract function
LIU Zhiwei
2020-08-28
softfloat: Implement the full set of comparisons for float16
Kito Cheng
2020-08-05
target/riscv/vector_helper: Fix build on 32-bit big endian hosts
Thomas Huth
2020-07-02
target/riscv: vector compress instruction
LIU Zhiwei
2020-07-02
target/riscv: vector register gather instruction
LIU Zhiwei
2020-07-02
target/riscv: vector slide instructions
LIU Zhiwei
2020-07-02
target/riscv: vector element index instruction
LIU Zhiwei
2020-07-02
target/riscv: vector iota instruction
LIU Zhiwei
2020-07-02
target/riscv: set-X-first mask bit
LIU Zhiwei
2020-07-02
target/riscv: vmfirst find-first-set mask bit
LIU Zhiwei
2020-07-02
target/riscv: vector mask population count vmpopc
LIU Zhiwei
2020-07-02
target/riscv: vector mask-register logical instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point reduction instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point reduction instructions
LIU Zhiwei
2020-07-02
target/riscv: vector wideing integer reduction instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width integer reduction instructions
LIU Zhiwei
2020-07-02
target/riscv: narrowing floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point merge instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point classify instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point compare instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point multiply
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
2020-07-02
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
2020-07-02
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
2020-07-02
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
2020-07-02
target/riscv: vector integer merge and move instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening integer multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width integer multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening integer multiply instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer divide instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width integer multiply instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer min/max instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer comparison instructions
LIU Zhiwei
2020-07-02
target/riscv: vector narrowing integer right shift instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width bit shift instructions
LIU Zhiwei
2020-07-02
target/riscv: vector bitwise logical instructions
LIU Zhiwei
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