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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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vector_helper.c
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Author
2023-10-12
target/riscv: Fix vfwmaccbf16.vf
Max Chou
2023-10-07
tcg: Correct invalid mentions of 'softmmu' by 'system-mode'
Philippe Mathieu-Daudé
2023-09-29
target/riscv: vector_helper: Fixup local variables shadowing
Alistair Francis
2023-09-11
target/riscv: Refactor some of the generic vector functionality
Kiran Ostrolenk
2023-09-11
target/riscv: Refactor some of the generic vector functionality
Kiran Ostrolenk
2023-09-11
target/riscv: Fix page_check_range use in fault-only-first
LIU Zhiwei
2023-08-31
target/translate: Include missing 'exec/cpu_ldst.h' header
Philippe Mathieu-Daudé
2023-08-24
include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()
Anton Johansson
2023-07-19
target/riscv: Fix LMUL check to use VLEN
Rob Bradford
2023-07-15
accel/tcg: Return bool from page_check_range
Richard Henderson
2023-07-10
target/riscv: Add support for Zvfbfwma extension
Weiwei Li
2023-07-10
target/riscv: Add support for Zvfbfmin extension
Weiwei Li
2023-06-13
target/riscv/vector_helper.c: Remove the check for extra tail elements
Xiao Wang
2023-06-13
target/riscv/vector_helper.c: clean up reference of MTYPE
Xiao Wang
2023-06-13
target/riscv: Fix pointer mask transformation for vector address
Weiwei Li
2023-06-13
target/riscv/vector_helper.c: skip set tail when vta is zero
Daniel Henrique Barboza
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
2023-03-01
target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig
Daniel Henrique Barboza
2023-03-01
target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
Daniel Henrique Barboza
2023-02-23
target/riscv: Fix vslide1up.vf and vslide1down.vf
LIU Zhiwei
2022-12-14
cleanup: Tweak and re-run return_directly.cocci
Markus Armbruster
2022-10-24
treewide: Remove the unnecessary space before semicolon
Bin Meng
2022-09-27
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
Yang Liu
2022-09-27
target/riscv: rvv-1.0: Simplify vfwredsum code
Yang Liu
2022-09-07
target/riscv: rvv: Add mask agnostic for vector permutation instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector mask instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector floating-point instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector integer shift instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vx instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector load / store instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vv instructions
Yueh-Ting (eop) Chen
2022-06-10
target/riscv: rvv: Add tail agnostic for vector permutation instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector mask instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector reduction instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector load / store instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vv instructions
eopXD
2022-06-10
target/riscv: rvv: Rename ambiguous esz
eopXD
2022-06-10
target/riscv: rvv: Prune redundant access_type parameter passed
eopXD
2022-06-10
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
eopXD
2022-04-22
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
Weiwei Li
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