slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-03-08	RISC-V: Add support for Ztso	Palmer Dabbelt
2024-02-09	target/riscv: Move misa_mxl_max to class	Akihiko Odaki
2024-01-29	target: Use vaddr in gen_intermediate_code	Anton Johansson
2024-01-10	target/riscv: Add support for Zacas extension	Weiwei Li
2023-10-04	accel/tcg: Replace CPUState.env_ptr with cpu_env()	Richard Henderson
2023-10-03	tcg: Rename cpu_env to tcg_env	Richard Henderson
2023-09-11	target/riscv: Add Zvbc ISA extension support	Lawrence Hunter
2023-07-10	riscv: Add support for the Zfa extension	Christoph Müllner
2023-07-10	target/riscv: Add support for Zfbfmin extension	Weiwei Li
2023-07-10	target/riscv: Add additional xlen for address when MPRV=1	Weiwei Li
2023-07-10	target/riscv: Factor out extension tests to cpu_cfg.h	Christoph Müllner
2023-06-13	target/riscv: Remove pc_succ_insn from DisasContext	Weiwei Li
2023-06-13	target/riscv: Enable PC-relative translation	Weiwei Li
2023-06-13	target/riscv: Use true diff for gen_pc_plus_diff	Weiwei Li
2023-06-13	target/riscv: Change gen_set_pc_imm to gen_update_pc	Weiwei Li
2023-06-13	target/riscv: Change gen_goto_tb to work on displacements	Weiwei Li
2023-06-13	target/riscv: Introduce cur_insn_len into DisasContext	Weiwei Li
2023-06-13	target/riscv: Fix target address to update badaddr	Weiwei Li
2023-06-13	target/riscv: Update check for Zca/Zcf/Zcd	Weiwei Li
2023-06-05	accel/tcg: Introduce translator_io_start	Richard Henderson
2023-06-05	tcg: Pass TCGHelperInfo to tcg_gen_callN	Richard Henderson
2023-05-05	target/riscv: Handle HLV, HSV via helpers	Richard Henderson
2023-05-05	target/riscv: Separate priv from mmu_idx	Fei Wu
2023-05-05	target/riscv: Add a tb flags field for vstart	LIU Zhiwei
2023-05-05	target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags	Richard Henderson
2023-05-05	target/riscv: Encode the FS and VS on a normal way for tb flags	LIU Zhiwei
2023-05-05	target/riscv: Extract virt enabled state from tb flags	LIU Zhiwei
2023-05-05	target/riscv: Fix format for comments	Weiwei Li
2023-05-05	target/riscv: Fix format for indentation	Weiwei Li
2023-05-05	target/riscv: Remove riscv_cpu_virt_enabled()	Weiwei Li
2023-05-05	target/riscv: Convert env->virt to a bool env->virt_enabled	LIU Zhiwei
2023-05-05	target/riscv: add support for Zcmp extension	Weiwei Li
2023-05-05	target/riscv: add support for Zcb extension	Weiwei Li
2023-05-05	target/riscv: add support for Zca extension	Weiwei Li
2023-03-07	Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...	Peter Maydell
2023-03-05	target/riscv: Avoid tcg_const_*	Richard Henderson
2023-03-05	target/riscv: Drop tcg_temp_free	Richard Henderson
2023-03-05	target/riscv: Drop temp_new	Richard Henderson
2023-03-05	target/riscv: Drop ftemp_new	Richard Henderson
2023-03-05	target/riscv: implement Zicboz extension	Christoph Muellner
2023-03-03	Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...	Peter Maydell
2023-03-01	target/riscv: Add support for Zicond extension	Weiwei Li
2023-03-01	target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages	Shaobo Song
2023-03-01	accel/tcg: Pass max_insn to gen_intermediate_code by pointer	Richard Henderson
2023-02-07	target/riscv: fix for virtual instr exception	Deepak Gupta
2023-02-07	RISC-V: Adding XTheadFmv ISA extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head FMemIdx extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head MemIdx extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head MemPair extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head multiply-accumulate instructions	Christoph Müllner