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path: root/target/riscv/translate.c
AgeCommit message (Expand)Author
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-09-01target/riscv: Clean up division helpersRichard Henderson
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang
2021-06-08target/riscv: rvb: generalized reverseFrank Chang
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng
2021-06-08target/riscv: rvb: shift onesKito Cheng
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng
2021-06-08target/riscv: rvb: count bits setFrank Chang
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer
2021-01-18riscv: Add semihosting supportKeith Packard
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson
2020-08-21meson: targetPaolo Bonzini
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée
2020-01-24Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung
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