slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson
2019-03-22	target/riscv: Zero extend the inputs of divuw and remuw	Palmer Dabbelt
2019-03-13	target/riscv: Remove decode_RV32_64G()	Bastian Koppelmann
2019-03-13	target/riscv: Remove gen_system()	Bastian Koppelmann
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64D insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64A insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann
2019-02-11	RISC-V: Add misa.MAFD checks to translate	Michael Clark
2019-02-11	RISC-V: Add misa to DisasContext	Michael Clark
2019-02-11	RISC-V: Add priv_ver to DisasContext	Alistair Francis
2019-02-11	RISC-V: Mark mstatus.fs dirty	Richard Henderson
2019-02-11	RISC-V: Split out mstatus_fs from tb_flags	Richard Henderson
2018-11-13	RISC-V: Respect fences for user-only emulators	Palmer Dabbelt
2018-11-13	target/riscv: Fix sfence.vm/a both available in any priv version	Bastian Koppelmann
2018-11-13	target/riscv: Fix FCLASS_D being treated as RV64 only	Bastian Koppelmann
2018-09-05	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	Emilio G. Cota
2018-09-05	target/riscv: optimize indirect branches	Emilio G. Cota
2018-09-05	target/riscv: optimize cross-page direct jumps in softmmu	Emilio G. Cota
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson
2018-05-11	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...	Peter Maydell
2018-05-10	target/riscv: Use new atomic min/max expanders	Richard Henderson
2018-05-09	target/riscv: convert to TranslatorOps	Emilio G. Cota
2018-05-09	target/riscv: convert to DisasContextBase	Emilio G. Cota
2018-05-09	target/riscv: convert to DisasJumpType	Emilio G. Cota
2018-05-09	target/riscv: avoid integer overflow in next_page PC check	Emilio G. Cota
2018-05-06	RISC-V: Add mcycle/minstret support for -icount auto	Michael Clark
2018-05-06	RISC-V: Remove erroneous comment from translate.c	Michael Clark
2018-03-07	RISC-V TCG Code Generation	Michael Clark