| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-11-07 | target/riscv: Add "pmu-mask" property to replace "pmu-num" | Rob Bradford |
| 2023-11-07 | target/riscv: Use existing PMU counter mask in FDT generation | Rob Bradford |
| 2023-11-07 | target/riscv: Propagate error from PMU setup | Rob Bradford |
| 2023-08-31 | target/riscv/pmu: Restrict 'qemu/log.h' include to source | Philippe Mathieu-Daudé |
| 2023-05-05 | target/riscv: Fix lines with over 80 characters | Weiwei Li |
| 2023-05-05 | target/riscv: Remove riscv_cpu_virt_enabled() | Weiwei Li |
| 2023-05-05 | target/riscv: fix invalid riscv,event-to-mhpmcounters entry | Conor Dooley |
| 2023-05-05 | target/riscv: Simplify type conversion for CPURISCVState | Weiwei Li |
| 2023-05-05 | target/riscv: Simplify getting RISCVCPU pointer from env | Weiwei Li |
| 2022-09-07 | hw/riscv: virt: Add PMU DT node to the device tree | Atish Patra |
| 2022-09-07 | target/riscv: Add sscofpmf extension support | Atish Patra |
| 2022-07-03 | target/riscv: Support mcycle/minstret write operation | Atish Patra |
 |
index : slackcoder/qemu | |
| QEMU is a generic and open source machine & userspace emulator and virtualizer | Mirror |
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