slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Collapse)	Author
2023-05-05	target/riscv: Fix lines with over 80 characters	Weiwei Li
	Fix lines with over 80 characters for both code and comments. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05	target/riscv: Remove riscv_cpu_virt_enabled()	Weiwei Li
	Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05	target/riscv: fix invalid riscv,event-to-mhpmcounters entry	Conor Dooley
	dt-validate complains: > soc: pmu: {'riscv,event-to-mhpmcounters': > [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], > [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]], > pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short There are bogus 0 entries added at the end, of which one is of insufficient length. This happens because only 15 of fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is called using the size of the array. Reduce the array to 15 elements to make the error go away. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230404173333.35179-1-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05	target/riscv: Simplify type conversion for CPURISCVState	Weiwei Li
	Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05	target/riscv: Simplify getting RISCVCPU pointer from env	Weiwei Li
	Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra
	Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra
	The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03	target/riscv: Support mcycle/minstret write operation	Atish Patra
	mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a initial value provided from supervisor OS. The Qemu also need prohibit the counter increment if mcountinhibit is set. Support mcycle/minstret through generic counter infrastructure. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>