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2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei
As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
Given the side effects they have, the csr instructions are realized as helpers. We extend this existing infrastructure for 128-bit sized csr. We return 128-bit values using the same approach as for div/rem. Theses helpers all call a unique function that is currently a fallback on the 64-bit version. The trans_csrxx functions supporting 128-bit are yet to be implemented. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-17-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin
As per the privilege specification, any access from S/U mode should fail if no pmp region is configured and pmp is present, othwerwise access should succeed. Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is configured) Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211214092659.15709-1-nikita.shubin@maquefel.me Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-08target/riscv: fix wfi exception behaviorJose Martins
The wfi exception trigger behavior should take into account user mode, hstatus.vtw, and the fact the an wfi might raise different types of exceptions depending on various factors: If supervisor mode is not present: - an illegal instruction exception should be generated if user mode executes and wfi instruction and mstatus.tw = 1. If supervisor mode is present: - when a wfi instruction is executed, an illegal exception should be triggered if either the current mode is user or the mode is supervisor and mstatus.tw is set. Plus, if the hypervisor extensions are enabled: - a virtual instruction exception should be raised when a wfi is executed from virtual-user or virtual-supervisor and hstatus.vtw is set. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210420213656.85148-1-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
Many files include qemu/log.h without needing it. Remove the superfluous include statements. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210328054833.2351597-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra
As per the privilege specification, any access from S/U mode should fail if no pmp region is configured. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201223192553.332508-1-atish.patra@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis
Split the hypervisor execute load functions into two seperate functions. This avoids us having to pass the memop to the C helper functions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 5b1550f0faa3c435cc77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis
Remove the special Virtulisation load and store functions and just use the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions instead. As part of this change we ensure we still run an access check to make sure we can perform the operations. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 189ac3e53ef2854824d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis
The HS_TWO_STAGE flag is no longer required as the MMU index contains the information if we are performing a two stage access. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: f514b128b1ff0fb41c85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis
When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: e411c61a1452cad16853f13cac2fb86dc91ebee8.1604464950.git.alistair.francis@wdc.com
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. This patch expands mstatus and vsstatus to uint64_t instead of target_ulong so that it can be saved as one unit and reduce some ifdefs in the code. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-2-jiangyifei@huawei.com
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer
The HLVX.WU instruction is supposed to read a machine word, but prior to this change it read a byte instead. Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions") Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201013172223.443645-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis
Currently we log interrupts and exceptions using the trace backend in riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log mask (-d int) in riscv_raise_exception(). This patch converts riscv_cpu_do_interrupt() to log both interrupts and exceptions with the interrupt log mask, so that both are printed when a user runs QEMU with -d int. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 29a8c766c7c4748d0f2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis
When performing a CSR access let's return a negative exception value on an error instead of -1. This will allow us to specify the exception in future patches. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com Message-Id: <a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com Message-Id: <e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since 4.1. It's not commonly used so let's remove support for it. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Behrens <jonathan@fintelia.io Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-01-16riscv: Set xPIE to 1 after xRETYiting Wang
When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly. Signed-off-by: Yiting Wang <yiting.wang@windriver.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson
Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-24target/riscv: Do not allow sfence.vma from user modeJonathan Behrens
The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
* Add riscv prefix to raise_exception function * Add riscv prefix to CSR read/write functions * Add riscv prefix to signal handler function * Add riscv prefix to get fflags function * Remove redundant declaration of riscv_cpu_init and rename cpu_riscv_init to riscv_cpu_init * rename riscv_set_mode to riscv_cpu_set_mode Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark
This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Co-authored-by: Matthew Suozzo <msuozzo@google.com> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
* Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark
This patch makes op_helper.c contain only instruction operation helpers used by translate.c and moves any unrelated cpu helpers into cpu_helper.c. No logic is changed by this patch. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
Change the API of riscv_set_local_interrupt to take a write mask and value to allow setting and clearing of multiple local interrupts atomically in a single call. Rename the new function to riscv_cpu_update_mip. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180606152128.449-11-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark
These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark
Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark
Previously the mycycle/minstret CSRs and rdcycle/rdinstret psuedo instructions would return the time as a proxy for an increasing instruction counter in the absence of having a precise instruction count. If QEMU is invoked with -icount, the mcycle/minstret CSRs and rdcycle/rdinstret psuedo instructions will return the instruction count. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark
Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >= v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <= v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >= v1.10 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark
The mstatus.MXR alias in sstatus should only be writable by S-mode if the privileged ISA version >= v1.10. Also MXR was masked in sstatus CSR read but not sstatus CSR writes. Now we correctly mask sstatus.mxr in both read and write. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark
satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-03-29RISC-V: Workaround for critical mstatus.FS bugMichael Clark
This change is a workaround for a bug where mstatus.FS is not correctly reporting dirty after operations that modify floating point registers. This a critical bug or RISC-V in QEMU as it results in floating point register file corruption when running SMP Linux due to task migration and possibly uniprocessor Linux if more than one process is using the FPU. This workaround will return dirty if mstatus.FS is switched from off to initial or clean. According to the specification it is legal for an implementation to return only off, or dirty. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-07RISC-V CPU HelpersMichael Clark
Privileged control and status register helpers and page fault handling. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
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