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path: root/target/riscv/op_helper.c
AgeCommit message (Expand)Author
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis
2020-01-16riscv: Set xPIE to 1 after xRETYiting Wang
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson
2019-05-24target/riscv: Do not allow sfence.vma from user modeJonathan Behrens
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark
2018-03-29RISC-V: Workaround for critical mstatus.FS bugMichael Clark
2018-03-07RISC-V CPU HelpersMichael Clark