aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/machine.c
AgeCommit message (Expand)Author
2023-12-29target/riscv: Constify VMState in machine.cRichard Henderson
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-04-22target/riscv: machine: Add debug state descriptionBin Meng
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2021-11-17target/riscv: machine: Sort the .subsectionsBin Meng
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-13 20:16:57 +0000