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path: root/target/riscv/machine.c
AgeCommit message (Expand)Author
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2021-11-17target/riscv: machine: Sort the .subsectionsBin Meng
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang
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