slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Collapse)	Author
2021-11-17	target/riscv: machine: Sort the .subsections	Bin Meng
	Move the codes around so that the order of .subsections matches the one they are referenced in vmstate_riscv_cpu. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211030030606.32297-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28	target/riscv: Add J extension state description	Alexey Baturo
	Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22	target/riscv: Split misa.mxl and misa.ext	Richard Henderson
	The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-11	target/riscv: Remove privilege v1.9 specific CSR related code	Atish Patra
	Qemu doesn't support RISC-V privilege specification v1.9. Remove the remaining v1.9 specific references from the implementation. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com> [Changes by AF: - Rebase on latest patches - Bump the vmstate_riscv_cpu version_id and minimum_version_id ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-11-03	target/riscv: Add V extension state description	Yifei Jiang
	In the case of supporting V extension, add V extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-6-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-11-03	target/riscv: Add H extension state description	Yifei Jiang
	In the case of supporting H extension, add H extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-5-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-11-03	target/riscv: Add PMP state description	Yifei Jiang
	In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. 'vmstate_pmp_addr' and 'num_rules' could be regenerated by pmp_update_rule(). But there exists the problem of updating num_rules repeatedly in pmp_update_rule(). So here extracts pmp_update_rule_addr() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-4-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-11-03	target/riscv: Add basic vmstate description of CPU	Yifei Jiang
	Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-3-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>