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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2023-02-07
RISC-V: Adding T-Head MemPair extension
Christoph Müllner
2023-02-07
RISC-V: Adding T-Head multiply-accumulate instructions
Christoph Müllner
2023-02-07
RISC-V: Adding XTheadCondMov ISA extension
Christoph Müllner
2023-02-07
RISC-V: Adding XTheadBs ISA extension
Christoph Müllner
2023-02-07
RISC-V: Adding XTheadBb ISA extension
Christoph Müllner
2023-02-07
RISC-V: Adding XTheadBa ISA extension
Christoph Müllner
2023-02-07
RISC-V: Adding XTheadSync ISA extension
Christoph Müllner
2023-02-07
RISC-V: Adding XTheadCmo ISA extension
Christoph Müllner
2023-02-07
target/riscv: Ensure opcode is saved for all relevant instructions
Anup Patel
2023-01-20
target/riscv: Introduce helper_set_rounding_mode_chkfrm
Richard Henderson
2023-01-06
RISC-V: Add Zawrs ISA extension support
Christoph Muellner
2023-01-06
target/riscv: Add itrigger support when icount is not enabled
LIU Zhiwei
2022-09-27
target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
Yang Liu
2022-09-13
target/riscv: Honour -semihosting-config userspace=on and enable=on
Peter Maydell
2022-09-07
target/riscv: Add Zihintpause support
Dao Lu
2022-09-07
target/riscv: rvv: Add mask agnostic for vector permutation instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector mask instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector floating-point instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector integer shift instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vx instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vector load / store instructions
Yueh-Ting (eop) Chen
2022-09-07
target/riscv: rvv: Add mask agnostic for vv instructions
Yueh-Ting (eop) Chen
2022-07-03
target/riscv: Minimize the calls to decode_save_opc
Richard Henderson
2022-07-03
target/riscv: Remove condition guarding register zero for auipc and lui
Víctor Colombo
2022-06-10
target/riscv: trans_rvv: Avoid assert for RV32 and e64
Alistair Francis
2022-06-10
target/riscv: rvv: Add tail agnostic for vector permutation instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector mask instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vector load / store instructions
eopXD
2022-06-10
target/riscv: rvv: Add tail agnostic for vv instructions
eopXD
2022-06-10
target/riscv: rvv: Early exit when vstart >= vl
eopXD
2022-06-10
target/riscv: add support for zmmul extension v0.1
Weiwei Li
2022-05-24
target/riscv: rvv: Fix early exit condition for whole register load/store
eopXD
2022-04-29
target/riscv: rvk: add support for zksed/zksh extension
Weiwei Li
2022-04-29
target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...
Weiwei Li
2022-04-29
target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...
Weiwei Li
2022-04-29
target/riscv: rvk: add support for sha256 related instructions in zknh extension
Weiwei Li
2022-04-29
target/riscv: rvk: add support for zkne/zknd extension in RV64
Weiwei Li
2022-04-29
target/riscv: rvk: add support for zknd/zkne extension in RV32
Weiwei Li
2022-04-29
target/riscv: rvk: add support for zbkx extension
Weiwei Li
2022-04-29
target/riscv: rvk: add support for zbkc extension
Weiwei Li
2022-04-29
target/riscv: rvk: add support for zbkb extension
Weiwei Li
2022-04-22
target/riscv: optimize helper for vmv<nr>r.v
Weiwei Li
2022-04-22
target/riscv: optimize condition assign for scale < 0
Weiwei Li
2022-04-06
Replace config-time define HOST_WORDS_BIGENDIAN
Marc-André Lureau
2022-04-01
target/riscv: rvv: Add missing early exit condition for whole register load/s...
Yueh-Ting (eop) Chen
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