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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2021-10-22
target/riscv: Use gen_unary_per_ol for RVB
Richard Henderson
2021-10-22
target/riscv: Adjust trans_rev8_32 for riscv64
Richard Henderson
2021-10-22
target/riscv: Use gen_arith_per_ol for RVM
Richard Henderson
2021-10-22
target/riscv: Replace DisasContext.w with DisasContext.ol
Richard Henderson
2021-10-22
target/riscv: Properly check SEW in amo_op
Richard Henderson
2021-10-22
target/riscv: Use REQUIRE_64BIT in amo_check64
Richard Henderson
2021-10-22
target/riscv: Fix orc.b implementation
Philipp Tomsich
2021-10-22
target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
Frank Chang
2021-10-15
target/riscv: Remove exit_tb and lookup_and_goto_ptr
Richard Henderson
2021-10-15
target/riscv: Remove dead code after exception
Richard Henderson
2021-10-07
target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
Philipp Tomsich
2021-10-07
target/riscv: Add rev8 instruction, removing grev/grevi
Philipp Tomsich
2021-10-07
target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Philipp Tomsich
2021-10-07
target/riscv: Reassign instructions to the Zbb-extension
Philipp Tomsich
2021-10-07
target/riscv: Add instructions of the Zbc-extension
Philipp Tomsich
2021-10-07
target/riscv: Reassign instructions to the Zbs-extension
Philipp Tomsich
2021-10-07
target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
Philipp Tomsich
2021-10-07
target/riscv: Remove the W-form instructions from Zbs
Philipp Tomsich
2021-10-07
target/riscv: Reassign instructions to the Zba-extension
Philipp Tomsich
2021-10-07
target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Philipp Tomsich
2021-10-07
target/riscv: fix clzw implementation to operate on arg1
Philipp Tomsich
2021-10-07
target/riscv: Introduce temporary in gen_add_uw()
Philipp Tomsich
2021-09-01
target/riscv: Use {get,dest}_gpr for RVV
Richard Henderson
2021-09-01
target/riscv: Tidy trans_rvh.c.inc
Richard Henderson
2021-09-01
target/riscv: Use {get,dest}_gpr for RVD
Richard Henderson
2021-09-01
target/riscv: Use {get,dest}_gpr for RVF
Richard Henderson
2021-09-01
target/riscv: Use gen_shift_imm_fn for slli_uw
Richard Henderson
2021-09-01
target/riscv: Use {get,dest}_gpr for RVA
Richard Henderson
2021-09-01
target/riscv: Reorg csr instructions
Richard Henderson
2021-09-01
target/riscv: Use {get, dest}_gpr for integer load/store
Richard Henderson
2021-09-01
target/riscv: Use get_gpr in branches
Richard Henderson
2021-09-01
target/riscv: Use extracts for sraiw and srliw
Richard Henderson
2021-09-01
target/riscv: Use DisasExtend in shift operations
Richard Henderson
2021-09-01
target/riscv: Add DisasExtend to gen_unary
Richard Henderson
2021-09-01
target/riscv: Move gen_* helpers for RVB
Richard Henderson
2021-09-01
target/riscv: Move gen_* helpers for RVM
Richard Henderson
2021-09-01
target/riscv: Use gen_arith for mulh and mulhu
Richard Henderson
2021-09-01
target/riscv: Remove gen_arith_div*
Richard Henderson
2021-09-01
target/riscv: Add DisasExtend to gen_arith*
Richard Henderson
2021-09-01
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
Richard Henderson
2021-09-01
target/riscv: Use tcg_constant_*
Richard Henderson
2021-06-08
target/riscv: rvb: add/shift with prefix zero-extend
Kito Cheng
2021-06-08
target/riscv: rvb: address calculation
Kito Cheng
2021-06-08
target/riscv: rvb: generalized or-combine
Frank Chang
2021-06-08
target/riscv: rvb: generalized reverse
Frank Chang
2021-06-08
target/riscv: rvb: rotate (left/right)
Kito Cheng
2021-06-08
target/riscv: rvb: shift ones
Kito Cheng
2021-06-08
target/riscv: rvb: single-bit instructions
Frank Chang
2021-06-08
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
Frank Chang
2021-06-08
target/riscv: rvb: sign-extend instructions
Kito Cheng
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