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AgeCommit message (Expand)Author
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich
2021-10-07target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang
2021-06-08target/riscv: rvb: generalized reverseFrank Chang
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng
2021-06-08target/riscv: rvb: shift onesKito Cheng
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng
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