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path: root/target/riscv/insn_trans
AgeCommit message (Expand)Author
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li
2022-03-03target/riscv: add support for zdinxWeiwei Li
2022-03-03target/riscv: add support for zfinxWeiwei Li
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
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