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AgeCommit message (Expand)Author
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
2021-12-20target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang
2021-12-20target/riscv: rvv-1.0: index load and store instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: stride load and store instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: configure instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang
2021-12-20target/riscv: rvv:1.0: add translation-time nan-box helper functionFrank Chang
2021-12-20target/riscv: introduce more imm value modes in translator functionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update check functionsFrank Chang
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang
2021-12-20target/riscv: zfh: half-precision floating-point classifyKito Cheng
2021-12-20target/riscv: zfh: half-precision floating-point compareKito Cheng
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng
2021-12-20target/riscv: zfh: half-precision computationalKito Cheng
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich
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