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QEMU is a generic and open source machine & userspace emulator and virtualizer
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insn_trans
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Author
2021-12-20
target/riscv: rvv-1.0: integer comparison instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width saturating add and subtract instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing integer right shift instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width bit shift instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer extension instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: whole register move instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point scalar move instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point move instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: integer scalar move instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: register gather instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: allow load element with sign-extended
Frank Chang
2021-12-20
target/riscv: rvv-1.0: iota instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: set-X-first mask bit instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: find-first-set mask bit instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: count population in mask instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
Frank Chang
2021-12-20
target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
Frank Chang
2021-12-20
target/riscv: rvv-1.0: load/store whole register instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: fault-only-first unit stride load
Frank Chang
2021-12-20
target/riscv: rvv-1.0: index load and store instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: stride load and store instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: configure instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove amo operations instructions
Frank Chang
2021-12-20
target/riscv: rvv:1.0: add translation-time nan-box helper function
Frank Chang
2021-12-20
target/riscv: introduce more imm value modes in translator functions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: update check functions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: remove MLEN calculations
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add translation-time vector context status
Frank Chang
2021-12-20
target/riscv: zfh: implement zfhmin extension
Frank Chang
2021-12-20
target/riscv: zfh: half-precision floating-point classify
Kito Cheng
2021-12-20
target/riscv: zfh: half-precision floating-point compare
Kito Cheng
2021-12-20
target/riscv: zfh: half-precision convert and move
Kito Cheng
2021-12-20
target/riscv: zfh: half-precision computational
Kito Cheng
2021-12-20
target/riscv: zfh: half-precision load and store
Kito Cheng
2021-10-28
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...
Alexey Baturo
2021-10-22
target/riscv: Use gen_shift*_per_ol for RVB, RVI
Richard Henderson
2021-10-22
target/riscv: Use gen_unary_per_ol for RVB
Richard Henderson
2021-10-22
target/riscv: Adjust trans_rev8_32 for riscv64
Richard Henderson
2021-10-22
target/riscv: Use gen_arith_per_ol for RVM
Richard Henderson
2021-10-22
target/riscv: Replace DisasContext.w with DisasContext.ol
Richard Henderson
2021-10-22
target/riscv: Properly check SEW in amo_op
Richard Henderson
2021-10-22
target/riscv: Use REQUIRE_64BIT in amo_check64
Richard Henderson
2021-10-22
target/riscv: Fix orc.b implementation
Philipp Tomsich
2021-10-22
target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
Frank Chang
2021-10-15
target/riscv: Remove exit_tb and lookup_and_goto_ptr
Richard Henderson
2021-10-15
target/riscv: Remove dead code after exception
Richard Henderson
2021-10-07
target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
Philipp Tomsich
2021-10-07
target/riscv: Add rev8 instruction, removing grev/grevi
Philipp Tomsich
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