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path: root/target/riscv/insn_trans
AgeCommit message (Expand)Author
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng
2021-06-08target/riscv: rvb: count bits setFrank Chang
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2021-01-18riscv: Add semihosting supportKeith Packard
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
2020-08-21target/riscv: check before allocating TCG tempsLIU Zhiwei
2020-08-21target/riscv: Clean up fmv.w.xLIU Zhiwei
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
2020-07-22target/riscv: fix vector index load/store constraintsLIU Zhiwei
2020-07-22target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei
2020-07-13target/riscv: fix return value of do_opivx_widen()Frank Chang
2020-07-13target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang
2020-07-13target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang
2020-07-02target/riscv: vector compress instructionLIU Zhiwei
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei
2020-07-02target/riscv: integer extract instructionLIU Zhiwei
2020-07-02target/riscv: vector element index instructionLIU Zhiwei
2020-07-02target/riscv: vector iota instructionLIU Zhiwei
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point min/max instructionsLIU Zhiwei
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