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AgeCommit message (Expand)Author
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson
2023-03-05target/riscv: Drop temp_newRichard Henderson
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01RISC-V: XTheadMemPair: Remove register restrictions for store-pairChristoph Müllner
2023-03-01target/riscv: Simplify check for EEW = 64 in trans_rvv.c.incWeiwei Li
2023-03-01target/riscv: Fix check for vector load/store instructions when EEW=64Weiwei Li
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
2023-03-01target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD
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