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path: root/target/riscv/insn_trans
AgeCommit message (Expand)Author
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening integer add and subtractLIU Zhiwei
2020-07-02target/riscv: vector single-width integer add and subtractLIU Zhiwei
2020-07-02target/riscv: add vector amo operationsLIU Zhiwei
2020-07-02target/riscv: add fault-only-first unit stride loadLIU Zhiwei
2020-07-02target/riscv: add vector index load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
2020-06-19riscv: Add helper to make NaN-boxing for FP registerIan Jiang
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-02-27target/riscv: Remove the hret instructionAlistair Francis
2020-02-27target/riscv: Add hfence instructionsAlistair Francis
2020-01-16target/riscv: fsd/fsw doesn't dirty FP stateShihPo Hung
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson
2019-05-24target/riscv: Use pattern groups in insn16.decodeRichard Henderson
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson
2019-05-24target/riscv: Merge argument sets for insn32 and insn16Richard Henderson
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau
2019-05-06decodetree: Add DisasContext argument to !function expandersRichard Henderson
2019-03-26target/riscv: Fix wrong expanding for c.fswspKito Cheng
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann
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