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path: root/target/riscv/insn_trans
AgeCommit message (Expand)Author
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li
2022-04-29target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li
2022-03-03target/riscv: add support for zdinxWeiwei Li
2022-03-03target/riscv: add support for zfinxWeiwei Li
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
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