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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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insn_trans
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trans_rvv.inc.c
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Author
2020-07-02
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point merge instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point classify instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point compare instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
2020-07-02
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point multiply
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
2020-07-02
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
2020-07-02
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
2020-07-02
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
2020-07-02
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
2020-07-02
target/riscv: vector integer merge and move instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening integer multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width integer multiply-add instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening integer multiply instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer divide instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width integer multiply instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer min/max instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer comparison instructions
LIU Zhiwei
2020-07-02
target/riscv: vector narrowing integer right shift instructions
LIU Zhiwei
2020-07-02
target/riscv: vector single-width bit shift instructions
LIU Zhiwei
2020-07-02
target/riscv: vector bitwise logical instructions
LIU Zhiwei
2020-07-02
target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
LIU Zhiwei
2020-07-02
target/riscv: vector widening integer add and subtract
LIU Zhiwei
2020-07-02
target/riscv: vector single-width integer add and subtract
LIU Zhiwei
2020-07-02
target/riscv: add vector amo operations
LIU Zhiwei
2020-07-02
target/riscv: add fault-only-first unit stride load
LIU Zhiwei
2020-07-02
target/riscv: add vector index load and store instructions
LIU Zhiwei
2020-07-02
target/riscv: add vector stride load and store instructions
LIU Zhiwei
2020-07-02
target/riscv: add vector configure instruction
LIU Zhiwei