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path: root/target/riscv/insn_trans/trans_rvv.c.inc
AgeCommit message (Expand)Author
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD
2022-04-22target/riscv: optimize helper for vmv<nr>r.vWeiwei Li
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang
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