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path: root/target/riscv/insn_trans/trans_rvm.inc.c
AgeCommit message (Expand)Author
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann