Age | Commit message (Expand) | Author |
---|---|---|
2019-03-22 | target/riscv: Zero extend the inputs of divuw and remuw | Palmer Dabbelt |
2019-03-13 | target/riscv: Rename trans_arith to gen_arith | Bastian Koppelmann |
2019-03-13 | target/riscv: Remove manual decoding of RV32/64M insn | Bastian Koppelmann |
2019-03-13 | target/riscv: Convert RVXM insns to decodetree | Bastian Koppelmann |