Age | Commit message (Expand) | Author |
---|---|---|
2022-06-10 | target/riscv: add support for zmmul extension v0.1 | Weiwei Li |
2022-01-08 | target/riscv: support for 128-bit M extension | Frédéric Pétrot |
2022-01-08 | target/riscv: support for 128-bit arithmetic instructions | Frédéric Pétrot |
2021-10-22 | target/riscv: Use gen_arith_per_ol for RVM | Richard Henderson |
2021-10-22 | target/riscv: Replace DisasContext.w with DisasContext.ol | Richard Henderson |
2021-09-01 | target/riscv: Move gen_* helpers for RVM | Richard Henderson |
2021-09-01 | target/riscv: Use gen_arith for mulh and mulhu | Richard Henderson |
2021-09-01 | target/riscv: Remove gen_arith_div* | Richard Henderson |
2021-09-01 | target/riscv: Add DisasExtend to gen_arith* | Richard Henderson |
2021-09-01 | target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr | Richard Henderson |
2021-05-11 | target/riscv: Consolidate RV32/64 32-bit instructions | Alistair Francis |
2020-08-21 | meson: rename included C source files to .c.inc | Paolo Bonzini |