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path: root/target/riscv/insn_trans/trans_rvi.inc.c
AgeCommit message (Expand)Author
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann