slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen
2019-08-20	icount: remove unnecessary gen_io_end calls	Pavel Dovgalyuk
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson
2019-05-24	RISC-V: fix single stepping over ret and other branching instructions	Fabien Chouteau
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann