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path: root/target/riscv/insn_trans/trans_rvi.c.inc
AgeCommit message (Expand)Author
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson
2022-07-03target/riscv: Remove condition guarding register zero for auipc and luiVíctor Colombo
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
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