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path: root/target/riscv/insn_trans/trans_rvf.c.inc
AgeCommit message (Expand)Author
2022-03-03target/riscv: add support for zfinxWeiwei Li
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2020-08-21target/riscv: check before allocating TCG tempsLIU Zhiwei
2020-08-21target/riscv: Clean up fmv.w.xLIU Zhiwei
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini