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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)Author
2020-07-02target/riscv: vector single-width fractional multiply with rounding and satur...LIU Zhiwei
2020-07-02target/riscv: vector single-width averaging add and subtractLIU Zhiwei
2020-07-02target/riscv: vector single-width saturating add and subtractLIU Zhiwei
2020-07-02target/riscv: vector integer merge and move instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening integer multiply-add instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width integer multiply-add instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening integer multiply instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer divide instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width integer multiply instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer min/max instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening integer add and subtractLIU Zhiwei
2020-07-02target/riscv: vector single-width integer add and subtractLIU Zhiwei
2020-07-02target/riscv: add vector amo operationsLIU Zhiwei
2020-07-02target/riscv: add fault-only-first unit stride loadLIU Zhiwei
2020-07-02target/riscv: add vector index load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
2020-02-27target/riscv: Remove the hret instructionAlistair Francis
2020-02-27target/riscv: Add hfence instructionsAlistair Francis
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann
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