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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)Author
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang
2021-06-08target/riscv: rvb: generalized reverseFrank Chang
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng
2021-06-08target/riscv: rvb: shift onesKito Cheng
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng
2021-06-08target/riscv: rvb: count bits setFrank Chang
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
2021-06-08target/riscv: reformat @sh format encoding for B-extensionKito Cheng
2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
2020-07-02target/riscv: vector compress instructionLIU Zhiwei
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei
2020-07-02target/riscv: integer extract instructionLIU Zhiwei
2020-07-02target/riscv: vector element index instructionLIU Zhiwei
2020-07-02target/riscv: vector iota instructionLIU Zhiwei
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei
2020-07-02target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point merge instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point classify instructionsLIU Zhiwei
2020-07-02target/riscv: vector floating-point compare instructionsLIU Zhiwei
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-03 23:40:16 +0000