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path: root/target/riscv/insn32.decode
AgeCommit message (Expand)Author
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li
2022-04-29target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: element index instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point classify instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point square-root instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang
2021-12-20target/riscv: rvv-1.0: index load and store instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: stride load and store instructionsFrank Chang
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