| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-05-24 | target/riscv: Add checks for several RVC reserved operands | Richard Henderson | |
| C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||
| 2019-05-24 | target/riscv: Split RVC32 and RVC64 insns into separate files | Richard Henderson | |
| This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||
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index : slackcoder/qemu | |
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