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path: root/target/riscv/helper.h
AgeCommit message (Expand)Author
2020-07-02target/riscv: vector widening integer multiply instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer divide instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width integer multiply instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer min/max instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening integer add and subtractLIU Zhiwei
2020-07-02target/riscv: vector single-width integer add and subtractLIU Zhiwei
2020-07-02target/riscv: add vector amo operationsLIU Zhiwei
2020-07-02target/riscv: add fault-only-first unit stride loadLIU Zhiwei
2020-07-02target/riscv: add vector index load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2018-03-07RISC-V CPU HelpersMichael Clark
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