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path: root/target/riscv/gdbstub.c
AgeCommit message (Expand)Author
2024-02-28gdbstub: Add members to identify registers to GDBFeatureAkihiko Odaki
2024-02-28gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cbAkihiko Odaki
2024-02-28gdbstub: Use GDBFeature for gdb_register_coprocessorAkihiko Odaki
2024-02-28target/riscv: Use GDBFeature for dynamic XMLAkihiko Odaki
2024-02-09target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...Conor Dooley
2024-02-09target/riscv: Move misa_mxl_max to classAkihiko Odaki
2024-02-09target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'Daniel Henrique Barboza
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée
2023-03-01target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xmlBin Meng
2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng
2022-09-27target/riscv: Check the correct exception cause in vector GDB stubFrank Chang
2022-09-27target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xmlAndrew Burgess
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2020-02-10riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard
2019-10-28target/riscv: Make the priv register writable by GDBJonathan Behrens
2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens
2019-10-28target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
2018-03-07RISC-V GDB StubMichael Clark
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