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2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée
These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
2023-03-01target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xmlBin Meng
It's worth noting that the vector CSR predicate() has a similar run-time check logic to the FPU CSR. With the previous patch our gdbstub can correctly report these vector CSRs via the CSR xml. Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 & rv32") inserted these vector CSRs in an ad-hoc, non-standard way in the riscv-vector.xml. Now we can treat these CSRs no different from other CSRs. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-13-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()Bin Meng
Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml") the 3 FPU CSRs are removed from the XML target decription. The original intent of that commit was based on the assumption that the 3 FPU CSRs will show up in the riscv-csr.xml so the ones in riscv-*-fpu.xml are redundant. But unforuantely that is not true. As the FPU CSR predicate() has a run-time check on MSTATUS.FS, at the time when CSR XML is generated MSTATUS.FS is unset, hence no FPU CSRs will be reported. The FPU CSR predicate() already considered such a case of being accessed by a debugger. All we need to do is to turn on debugger mode before calling predicate(). Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-12-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabledBin Meng
There is no need to generate the CSR XML if the Zicsr extension is not enabled. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-6-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Minor change for better readabilityBin Meng
Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-5-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: gdbstub: Check priv spec version before reporting CSRBin Meng
The gdbstub CSR XML is dynamically generated according to the result of the CSR predicate() result. This has been working fine until commit 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") introduced the privilege spec version check in riscv_csrrw_check(). When debugging the 'sifive_u' machine whose priv spec is at 1.10, gdbstub reports priv spec 1.12 CSRs like menvcfg in the XML, hence we see "remote failure reply 'E14'" message when examining all CSRs via "info register system" from gdb. Add the priv spec version check in the CSR XML generation logic to fix this issue. Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-2-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-09-27target/riscv: Check the correct exception cause in vector GDB stubFrank Chang
After RISCVException enum is introduced, riscv_csrrw_debug() returns RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub should check the result against RISCV_EXCP_NONE instead of value 0. Otherwise, 'E14' packet would be incorrectly reported for vector CSRs when using "info reg vector" GDB command. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20220918083245.13028-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xmlAndrew Burgess
While testing some changes to GDB's handling for the RISC-V registers fcsr, fflags, and frm, I spotted that QEMU includes these registers twice in the target description it sends to GDB, once in the fpu feature, and once in the csr feature. Right now things basically work OK, QEMU maps these registers onto two different register numbers, e.g. fcsr maps to both 68 and 73, and GDB can use either of these to access the register. However, GDB's target descriptions don't really work this way, each register should appear just once in a target description, mapping the register name onto the number GDB should use when accessing the register on the target. Duplicate register names actually result in duplicate registers on the GDB side, however, as the registers have the same name, the user can only access one of these registers. Currently GDB has a hack in place, specifically for RISC-V, to spot the duplicate copies of these three registers, and hide them from the user, ensuring the user only ever sees a single copy of each. In this commit I propose fixing this issue on the QEMU side, and in the process, simplify the fpu register handling a little. I think we should, remove fflags, frm, and fcsr from the two (32-bit and 64-bit) fpu feature xml files. These files will only contain the 32 core floating point register f0 to f31. The fflags, frm, and fcsr registers will continue to be advertised in the csr feature as they currently are. With that change made, I will simplify riscv_gdb_get_fpu and riscv_gdb_set_fpu, removing the extra handling for the 3 status registers. Signed-off-by: Andrew Burgess <aburgess@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot
The addition of uxl support in gdbstub adds a few checks on the maximum register length, but omitted MXL_RV128, an experimental feature. This patch makes rv128 react as rv64, as previously. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
This patch adds the support of the '-cpu rv128' option to qemu-system-riscv64 so that we can indicate that we want to run rv128 executables. Still, there is no support for 128-bit insns at that stage so qemu fails miserably (as expected) if launched with this option. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr [ Changed by AF - Rename CPU to "x-rv128" ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-69-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng
Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations") the CSR predicate() function was changed to return RISCV_EXCP_NONE instead of 0 for a valid CSR, but it forgot to update the dynamic CSR XML generation codes in gdbstub. Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR operations") Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
At present QEMU RISC-V uses a hardcoded XML to report the feature "org.gnu.gdb.riscv.csr" [1]. There are two major issues with the approach being used currently: - The XML does not specify the "regnum" field of a CSR entry, hence consecutive numbers are used by the remote GDB client to access CSRs. In QEMU we have to maintain a map table to convert the GDB number to the hardware number which is error prone. - The XML contains some CSRs that QEMU does not implement at all, which causes an "E14" response sent to remote GDB client. Change to generate the CSR register list dynamically, based on the availability presented in the CSR function table. This new approach will reflect a correct list of CSRs that QEMU actually implements. [1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée
Instead of passing a pointer to memory now just extend the GByteArray to all the read register helpers. They can then safely append their data through the normal way. We don't bother with this abstraction for write registers as we have already ensured the buffer being copied from is the correct size. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-Id: <20200316172155.971-15-alex.bennee@linaro.org>
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
Add the Hypervisor CSRs to CPUState and at the same time (to avoid bisect issues) update the CSR macros for the v0.5 Hyp spec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-10riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard
The size of the FPU registers is dictated by the 'f' and 'd' features, not the core processor register size. Processors with the 'd' feature have 64-bit FPU registers. Processors without the 'd' feature but with the 'f' feature have 32-bit FPU registers. Signed-off-by: Keith Packard <keithp@keithp.com> [Palmer: This requires manually triggering a rebuild of riscv32-softmmu/gdbstub-xml.c] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2019-10-28target/riscv: Make the priv register writable by GDBJonathan Behrens
Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that the privilege mode is set to one of them. Once support for the H-extension is added, this code will also need to properly update the virtualization status when switching between VU/VS-modes and M-mode. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens
This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens
If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic
While debugging an application with GDB the following might happen: (gdb) return Make xxx return now? (y or n) y Could not fetch register "fflags"; remote failure reply 'E14' This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr number (8). It should use the csr_register_map in order to reach the riscv_cpu_get_fflags callback. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson
The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds fairly standard gdb hooks to access xml specified registers. notice: The fpu xml from gdb 8.3 has unused register #, 65 and make first csr register # become 69. We register extra register on gdb to correct csr offset calculation Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-03-07RISC-V GDB StubMichael Clark
GDB Register read and write routines. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
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