| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-09-27 | target/riscv: debug: Add initial support of type 6 trigger | Frank Chang |
| 2022-09-27 | target/riscv: debug: Create common trigger actions function | Frank Chang |
| 2022-09-27 | target/riscv: debug: Introduce tinfo CSR | Frank Chang |
| 2022-09-27 | target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs | Frank Chang |
| 2022-09-27 | target/riscv: debug: Introduce build_tdata1() to build tdata1 register content | Frank Chang |
| 2022-09-27 | target/riscv: debug: Determine the trigger type from tdata1.type | Frank Chang |
| 2022-04-22 | target/riscv: csr: Hook debug CSR read/write | Bin Meng |
| 2022-04-22 | target/riscv: debug: Implement debug related TCGCPUOps | Bin Meng |
| 2022-04-22 | target/riscv: Add initial support for the Sdtrig extension | Bin Meng |
 |
index : slackcoder/qemu | |
| QEMU is a generic and open source machine & userspace emulator and virtualizer | Mirror |
| aboutsummaryrefslogtreecommitdiff |