slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-09-11	target/riscv: Allocate itrigger timers only once	Akihiko Odaki
2023-09-08	riscv: spelling fixes	Michael Tokarev
2023-05-05	target/riscv: Fix lines with over 80 characters	Weiwei Li
2023-05-05	target/riscv: Remove riscv_cpu_virt_enabled()	Weiwei Li
2023-02-07	target/riscv: set tval for triggered watchpoints	Sergey Matyukevich
2023-01-06	target/riscv: Add itrigger_enabled field to CPURISCVState	LIU Zhiwei
2023-01-06	target/riscv: Enable native debug itrigger	LIU Zhiwei
2023-01-06	target/riscv: Add itrigger support when icount is enabled	LIU Zhiwei
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei
2022-12-14	cleanup: Tweak and re-run return_directly.cocci	Markus Armbruster
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang
2022-09-27	target/riscv: debug: Check VU/VS modes for type 2 trigger	Frank Chang
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang
2022-09-27	target/riscv: debug: Restrict the range of tselect value can be written	Frank Chang
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang
2022-06-10	target/riscv/debug.c: keep experimental rv128 support working	Frédéric Pétrot
2022-04-22	target/riscv: csr: Hook debug CSR read/write	Bin Meng
2022-04-22	target/riscv: debug: Implement debug related TCGCPUOps	Bin Meng
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng