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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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debug.c
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Commit message (
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Author
2023-01-06
target/riscv: Add itrigger support when icount is not enabled
LIU Zhiwei
2022-12-14
cleanup: Tweak and re-run return_directly.cocci
Markus Armbruster
2022-09-27
target/riscv: debug: Add initial support of type 6 trigger
Frank Chang
2022-09-27
target/riscv: debug: Check VU/VS modes for type 2 trigger
Frank Chang
2022-09-27
target/riscv: debug: Create common trigger actions function
Frank Chang
2022-09-27
target/riscv: debug: Introduce tinfo CSR
Frank Chang
2022-09-27
target/riscv: debug: Restrict the range of tselect value can be written
Frank Chang
2022-09-27
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
Frank Chang
2022-09-27
target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
Frank Chang
2022-09-27
target/riscv: debug: Determine the trigger type from tdata1.type
Frank Chang
2022-06-10
target/riscv/debug.c: keep experimental rv128 support working
Frédéric Pétrot
2022-04-22
target/riscv: csr: Hook debug CSR read/write
Bin Meng
2022-04-22
target/riscv: debug: Implement debug related TCGCPUOps
Bin Meng
2022-04-22
target/riscv: Add initial support for the Sdtrig extension
Bin Meng