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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2023-03-01target/riscv: Allow debugger to access {h, s}stateen CSRsBin Meng
2023-03-01target/riscv: Allow debugger to access seed CSRBin Meng
2023-03-01target/riscv: Allow debugger to access user timer and counter CSRsBin Meng
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng
2023-03-01target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...Bin Meng
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza
2023-03-01target/riscv: do not mask unsupported QEMU extensions in write_misa()Daniel Henrique Barboza
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
2023-01-20target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker
2023-01-20target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang
2022-09-27target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li
2022-09-07target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra
2022-09-07target/riscv: Simplify counter predicate functionAtish Patra
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: Remove additional priv version check for mcountinhibitAtish Patra
2022-09-07target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li
2022-09-07target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li
2022-09-07target/riscv: Add check for csrs existed with U extensionWeiwei Li
2022-09-07target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra
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