aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/csr.c
AgeCommit message (Collapse)Author
2023-05-10target/riscv: Restore the predicate() NULL check behaviorBin Meng
When reading a non-existent CSR QEMU should raise illegal instruction exception, but currently it just exits due to the g_assert() check. This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617. Some comments are also added to indicate that predicate() must be provided for an implemented CSR. Reported-by: Fei Wu <fei2.wu@intel.com> Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> (cherry picked from commit eae04c4c131a8d95087c8568eb2cac1988262f25) (mjt: context edit after ce3af0bbbcdfa "target/riscv: add support for Zcmt extension") Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-03-07includes: move tb_flush into its own headerAlex Bennée
This aids subsystems (like gdbstub) that want to trigger a flush without pulling target specific headers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-8-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-8-richard.henderson@linaro.org>
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry <ludovic@rivosinc.com> Signed-off-by: Ludovic Henry <ludovic@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-4-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Change type of valid_vm_1_10_[32|64] to boolAlexandre Ghiti
This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-3-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01Merge patch series "RISCVCPUConfig related cleanups"Palmer Dabbelt
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says: These cleanups were suggested by LIU Zhiwei during the review of d3e6d5762b ("Merge patch series "make write_misa a no-op and FEATURE_* cleanups""). * b4-shazam-merge: target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers target/riscv/csr.c: simplify mctr() target/riscv/csr.c: use env_archcpu() in ctr() Message-ID: <20230224174520.92490-1-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza
Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg can be avoided by using riscv_cpu_cfg(). Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230224174520.92490-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointersDaniel Henrique Barboza
A common trend in this file is to retrieve a RISCVCPU pointer by first retrieving a CPUState pointer via env_cpu(). The CPU pointer is used only to access the RISCVCPUConfig object and nothing else. Let's use riscv_cpu_cfg() to access what we need directly without these 2 pointers. Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230224174520.92490-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv/csr.c: simplify mctr()Daniel Henrique Barboza
Use riscv_cpu_cfg() to retrieve pmu_num. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230224174520.92490-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv/csr.c: use env_archcpu() in ctr()Daniel Henrique Barboza
We don't need to use env_cpu() and CPUState(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230224174520.92490-2-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
Weiwei Li <liweiwei@iscas.ac.cn> says: This patchset adds support svadu extension. It also fixes some relationship between *envcfg fields and Svpbmt/Sstc extensions. Specification for Svadu extension can be found in: https://github.com/riscv/riscv-svadu * b4-shazam-merge: target/riscv: Export Svadu property target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add csr support for svadu target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Message-ID: <20230224040852.37109-1-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
Add ext_svadu property Add HADE field in *envcfg: * menvcfg.HADE is read-only zero if Svadu is not implemented. * henvcfg.HADE is read-only zero if menvcfg.HADE is zero. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and ↵Weiwei Li
henvcfg henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-3-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and ↵Weiwei Li
Svpbmt/Sstc extensions menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-2-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"Palmer Dabbelt
Bin Meng <bmeng@tinylab.org> says: At present gdbstub reports an incorrect / incomplete CSR list in the target description XML, for example: - menvcfg is reported in 'sifive_u' machine - fcsr is missing in a F/D enabled processor The issue is caused by: - priv spec version check is missing when reporting CSRs - CSR predicate() routine is called without turning on the debugger flag * b4-shazam-merge: target/riscv: Group all predicate() routines together target/riscv: Drop priv level check in mseccfg predicate() target/riscv: Allow debugger to access sstc CSRs target/riscv: Allow debugger to access {h, s}stateen CSRs target/riscv: Allow debugger to access seed CSR target/riscv: Allow debugger to access user timer and counter CSRs target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 target/riscv: Simplify getting RISCVCPU pointer from env target/riscv: Simplify {read, write}_pmpcfg() a little bit target/riscv: Use 'bool' type for read_only target/riscv: Coding style fixes in csr.c target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled target/riscv: gdbstub: Minor change for better readability target/riscv: Use g_assert() for the predicate() NULL check target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() target/riscv: gdbstub: Check priv spec version before reporting CSR Message-ID: <20230228104035.1879882-1-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Group all predicate() routines togetherBin Meng
Move sstc()/sstc32() to where all predicate() routines live, and smstateen_acc_ok() to near {read,write}_xenvcfg(). Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-19-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Drop priv level check in mseccfg predicate()Bin Meng
riscv_csrrw_check() already does the generic privilege level check hence there is no need to do the specific M-mode access check in the mseccfg predicate(). With this change debugger can access the mseccfg CSR anytime. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-18-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Allow debugger to access sstc CSRsBin Meng
At present with a debugger attached sstc CSRs can only be accssed when CPU is in M-mode, or configured correctly. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as adding a debugger check. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-17-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Allow debugger to access {h, s}stateen CSRsBin Meng
At present {h,s}stateen CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as adding a debugger check. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-16-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Allow debugger to access seed CSRBin Meng
At present seed CSR is not reported in the CSR XML hence gdb cannot access it. Fix it by adding a debugger check in its predicate() routine. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-15-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Allow debugger to access user timer and counter CSRsBin Meng
At present user timer and counter CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adding a debugger check in their predicate() routine. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-14-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64Bin Meng
At present the odd-numbered PMP configuration registers for RV64 are reported in the CSR XML by QEMU gdbstub. However these registers do not exist on RV64 so trying to access them from gdb results in 'E14'. Move the pmpcfgX index check from the actual read/write routine to the PMP CSR predicate() routine, so that non-existent pmpcfgX won't be reported in the CSR XML for RV64. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-11-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify getting RISCVCPU pointer from envBin Meng
Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-10-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify {read, write}_pmpcfg() a little bitBin Meng
Use the register index that has already been calculated in the pmpcfg_csr_{read,write} call. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-9-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Use 'bool' type for read_onlyBin Meng
The read_only variable is currently declared as an 'int', but it should really be a 'bool'. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-8-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Coding style fixes in csr.cBin Meng
Fix various places that violate QEMU coding style: - correct multi-line comment format - indent to opening parenthesis Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-7-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Use g_assert() for the predicate() NULL checkBin Meng
At present riscv_csrrw_check() checks the CSR predicate() against NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is a pure software check, and has nothing to do with the emulation of the hardware behavior, thus it is inappropriate to return illegal instruction exception when software forgets to install the hook. Change to use g_assert() instead. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-4-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Add some comments to clarify the priority policy of ↵Bin Meng
riscv_csrrw_check() The priority policy of riscv_csrrw_check() was once adjusted in commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check") whose commit message says the CSR existence check should come before the access control check, but the code changes did not agree with the commit message, that the predicate() check actually came after the read / write check. In fact this was intentional. Add some comments there so that people won't bother trying to change it without a solid reason. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Message-ID: <20230228104035.1879882-3-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01Merge patch series "target/riscv: Some updates to float point related ↵Palmer Dabbelt
extensions" RISC-V defines a handful of extensions related to floating point, along with various relationships between these and other extensions. This patch set adds support for the Zvfh, Zvhfmin, and Zve64d extensions; along with a handful of fixes and cleanups related to the other floating-point extension relationships. * b4-shazam-merge target/riscv: Expose properties for Zv* extensions target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc target/riscv: Fix check for vector load/store instructions when EEW=64 target/riscv: Add support for Zvfh/zvfhmin extensions target/riscv: Remove rebundunt check for zve32f and zve64f target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc target/riscv: Simplify check for Zve32f and Zve64f target/riscv: Indent fixes in cpu.c target/riscv: Add propertie check for Zvfh{min} extensions target/riscv: Fix relationship between V, Zve*, F and D target/riscv: Add cfg properties for Zv* extensions target/riscv: Simplify the check for Zfhmin and Zhinxmin target/riscv: Fix the relationship between Zhinxmin and Zhinx target/riscv: Fix the relationship between Zfhmin and Zfh Message-ID: <20230215020539.4788-1-liweiwei@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-10-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza
At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will always exit earlier. This seems to be benign in the majority of cases. Booting an Ubuntu 'virt' guest and logging all the calls to 'write_misa' shows that no writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling RISC-V extensions after the machine is powered on, seems to be a niche use. After discussions in the mailing list, most notably in [1], we reached the consensus that this code is not suited to be exposed to users because it's not well tested, but at the same time removing it is a bit extreme because we would like to fix it, and it's easier to do so with the code available to use instead of fetching it from git log. The approach taken here is to get rid of RISCV_FEATURE_MISA altogether and use a new experimental flag called x-misa-w. The default value is false, meaning that we're keeping the existing behavior of doing nothing if a write_misa() is attempted. As with any existing experimental flag, x-misa-w is also a temporary flag that we need to remove once we fix write_misa(). [1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-01target/riscv: do not mask unsupported QEMU extensions in write_misa()Daniel Henrique Barboza
The masking done using env->misa_ext_mask already filters any extension that QEMU doesn't support. If the hart supports the extension then QEMU supports it as well. If the masking done by env->misa_ext_mask is somehow letting unsupported QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230222185205.355361-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
The RVV specification does not require that the core needs to support the privileged specification v1.12.0 to support RVV, and there is no dependency from ISA level. This commit removes the restriction from both RVV CSRs and extension CPU ISA string. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230208063209.27279-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
The htimedelta[h] CSR has impact on the VS timer comparison so we should call riscv_timer_write_timecmp() whenever htimedelta changes. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-20target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker
Per the AIA specification, writes to stimecmp from VS level should trap when hvictl.VTI is set since the write may cause vsip.STIP to become unset. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-20target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker
The current logic attempts to shift the VS-level bits into their correct position in mip while leaving the remaining bits in-tact. This is both pointless and likely incorrect since one would expect that any new, future VS-level interrupts will get their own position in mip rather than sharing with their (H)S-level equivalent. Fix this, and make the logic more readable, by just making off the VS-level bits and shifting them into position. This also fixes reads of vsip, which would only ever report vsip.VSSIP since the non-writable bits got masked off as well. Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32") Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
We should use "&&" instead of "&" when checking hcounteren.TM and henvcfg.STCE bits. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale
Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221016124726.102129-3-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221016124726.102129-2-mchitale@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang
tinfo.info: One bit for each possible type enumerated in tdata1. If the bit is set, then that type is supported by the currently selected trigger. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang
Current RISC-V debug assumes that only type 2 trigger is supported. To allow more types of triggers to be supported in the future (e.g. type 6 trigger, which is similar to type 2 trigger with additional functionality), we should determine the trigger type from tdata1.type. RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> [bmeng: fixed MXL_RV128 case, and moved macros to the following patch] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li
- modify check for mcounteren to work in all less-privilege mode - modify check for scounteren to work only when S mode is enabled - distinguish the exception type raised by check for scounteren between U and VU mode Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra
The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Simplify counter predicate functionAtish Patra
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add stimecmp supportAtish Patra
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 23:31:38 +0000