aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Add support for mconfigptrAtish Patra
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra
2022-04-01target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt
2022-03-06misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng
2021-09-21target/riscv: Fix satp writeLIU Zhiwei
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-11 02:23:36 +0000