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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-09-21target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng
2021-09-21target/riscv: Fix satp writeLIU Zhiwei
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng
2021-07-15target/riscv: hardwire bits in hideleg and hedelegJose Martins
2021-07-15target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
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