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path: root/target/riscv/csr.c
AgeCommit message (Expand)Author
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
2023-01-20target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker
2023-01-20target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2022-09-27target/riscv: debug: Introduce tinfo CSRFrank Chang
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang
2022-09-27target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}Weiwei Li
2022-09-07target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra
2022-09-07target/riscv: Simplify counter predicate functionAtish Patra
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: Remove additional priv version check for mcountinhibitAtish Patra
2022-09-07target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li
2022-09-07target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li
2022-09-07target/riscv: Add check for csrs existed with U extensionWeiwei Li
2022-09-07target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra
2022-07-03target/riscv: Implement PMU CSR predicate function for S-modeAtish Patra
2022-07-03target/riscv: Fix PMU CSR predicate functionAtish Patra
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: Fix VS mode hypervisor CSR accessDylan Reid
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Add support for mconfigptrAtish Patra
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra
2022-04-01target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt
2022-03-06misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel
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