Age | Commit message (Expand) | Author |
2021-01-16 | target/riscv: Add CSR name in the CSR function table | Bin Meng |
2021-01-16 | target/riscv: Make csr_ops[CSR_TABLE_SIZE] external | Bin Meng |
2020-12-17 | target/riscv: csr: Remove compile time XLEN checks | Alistair Francis |
2020-11-03 | target/riscv/csr.c : add space before the open parenthesis '(' | Xinhao Zhang |
2020-11-03 | target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit | Yifei Jiang |
2020-10-05 | icount: rename functions to be consistent with the module name | Claudio Fontana |
2020-10-05 | cpu-timers, icount: new modules | Claudio Fontana |
2020-09-09 | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng |
2020-08-25 | target/riscv: Support the Virtual Instruction fault | Alistair Francis |
2020-08-25 | target/riscv: Return the exception from invalid CSR accesses | Alistair Francis |
2020-08-25 | target/riscv: Support the v0.6 Hypervisor extension CRSs | Alistair Francis |
2020-08-25 | target/riscv: Only support little endian guests | Alistair Francis |
2020-08-25 | target/riscv: Only support a single VSXL length | Alistair Francis |
2020-08-25 | target/riscv: Convert MSTATUS MTL to GVA | Alistair Francis |
2020-08-25 | target/riscv: Don't allow guest to write to htinst | Alistair Francis |
2020-07-22 | target/riscv: Fix the range of pmpcfg of CSR funcion table | Zong Li |
2020-07-02 | target/riscv: support vector extension csr | LIU Zhiwei |
2020-06-03 | target/riscv: Drop support for ISA spec version 1.09.1 | Alistair Francis |
2020-02-27 | target/riscv: Emulate TIME CSRs for privileged mode | Anup Patel |
2020-02-27 | target/riscv: Add support for the 32-bit MSTATUSH CSR | Alistair Francis |
2020-02-27 | target/riscv: Extend the SIP CSR to support virtulisation | Alistair Francis |
2020-02-27 | target/riscv: Extend the MIE CSR to support virtulisation | Alistair Francis |
2020-02-27 | target/riscv: Set VS bits in mideleg for Hyp extension | Alistair Francis |
2020-02-27 | target/riscv: Add Hypervisor machine CSRs accesses | Alistair Francis |
2020-02-27 | target/riscv: Add Hypervisor virtual CSRs accesses | Alistair Francis |
2020-02-27 | target/riscv: Add Hypervisor CSR access functions | Alistair Francis |
2020-02-27 | target/riscv: Fix CSR perm checking for HS mode | Alistair Francis |
2020-02-27 | target/riscv: Add support for the new execption numbers | Alistair Francis |
2020-01-16 | target/riscv: update mstatus.SD when FS is set dirty | ShihPo Hung |
2019-11-14 | target/riscv: Remove atomic accesses to MIP CSR | Alistair Francis |
2019-10-28 | riscv: Skip checking CSR privilege level in debugger mode | Bin Meng |
2019-09-17 | target/riscv: Fix mstatus dirty mask | Alistair Francis |
2019-09-17 | target/riscv: Create function to test if FP is enabled | Alistair Francis |
2019-06-25 | RISC-V: Add support for the Zicsr extension | Palmer Dabbelt |
2019-06-25 | target/riscv: Add support for disabling/enabling Counters | Alistair Francis |
2019-06-25 | target/riscv: Add the mcountinhibit CSR | Alistair Francis |
2019-06-10 | target/riscv: Use env_cpu, env_archcpu | Richard Henderson |
2019-05-24 | target/riscv: Only flush TLB if SATP.ASID changes | Jonathan Behrens |
2019-05-24 | target/riscv: More accurate handling of `sip` CSR | Jonathan Behrens |
2019-05-24 | target/riscv: Allow setting mstatus virtulisation bits | Alistair Francis |
2019-05-24 | target/riscv: Trigger interrupt on MIP update asynchronously | Alistair Francis |
2019-03-19 | RISC-V: Add support for vectored interrupts | Michael Clark |
2019-03-19 | RISC-V: Allow interrupt controllers to claim interrupts | Michael Clark |
2019-03-19 | RISC-V: Add debug support for accessing CSRs. | Jim Wilson |
2019-02-11 | target/riscv: fix counter-enable checks in ctr() | Xi Wang |
2019-02-11 | RISC-V: Add misa runtime write support | Michael Clark |
2019-02-11 | RISC-V: Use riscv prefix consistently on cpu helpers | Michael Clark |
2019-02-11 | RISC-V: Implement mstatus.TSR/TW/TVM | Michael Clark |
2019-02-11 | RISC-V: Mark mstatus.fs dirty | Richard Henderson |
2019-01-09 | RISC-V: Implement existential predicates for CSRs | Michael Clark |