aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)Author
2023-10-12target/riscv: Use env_archcpu for better performanceRichard W.M. Jones
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li
2023-07-10target/riscv: Set the correct exception for implict G-stage translation failJason Chien
2023-07-10target/riscv: update cur_pmbase/pmmask based on mode affected by MPRVWeiwei Li
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li
2023-07-10target/riscv: Make MPV only work when MPP != PRV_MWeiwei Li
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson
2023-06-13target/riscv: Fix initialized value for cur_pmmaskWeiwei Li
2023-06-13target/riscv: Reuse tb->flags.FSMayuresh Chitale
2023-06-13target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li
2023-06-13target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmpWeiwei Li
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li
2023-06-05tcg: Split out tcg/oversized-guest.hRichard Henderson
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova
2023-05-05target/riscv: Reorg sum check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Reorg access check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Merge checks for reserved pte flagsRichard Henderson
2023-05-05target/riscv: Don't modify SUM with is_debugRichard Henderson
2023-05-05target/riscv: Suppress pte update with is_debugRichard Henderson
2023-05-05target/riscv: Move leaf pte processing out of level loopRichard Henderson
2023-05-05target/riscv: Hoist pbmte and hade out of the level loopRichard Henderson
2023-05-05target/riscv: Hoist second stage mode change to callersRichard Henderson
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_privRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_sumRichard Henderson
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-17 04:46:23 +0000