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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)Author
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova
2023-05-05target/riscv: Reorg sum check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Reorg access check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Merge checks for reserved pte flagsRichard Henderson
2023-05-05target/riscv: Don't modify SUM with is_debugRichard Henderson
2023-05-05target/riscv: Suppress pte update with is_debugRichard Henderson
2023-05-05target/riscv: Move leaf pte processing out of level loopRichard Henderson
2023-05-05target/riscv: Hoist pbmte and hade out of the level loopRichard Henderson
2023-05-05target/riscv: Hoist second stage mode change to callersRichard Henderson
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_privRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_sumRichard Henderson
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
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